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application/pdf
MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications
Freescale Semiconductor, Inc.
This document provides an overview of the MPC8360E/58E PowerQUICC II Pro processor revision 2.x TBGA features, including a block diagram showing the major functional components. This device is a cost-effective, highly integrated communications processor that addresses the needs of the networking, wireless infrastructure, and
telecommunications markets.
2011
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(M9.40746.FigTitle.Figure23..ALTERNATE.JTAG.Clock.Input.Timing.Diagram) 1777 0 R (M9.40778.FigTitle.Figure54.PPC8360EMPC8360E.Clock.Subsystem) 1778 0 R (M9.40872.TBItemNum.2.This.symbol.is.used.to.represent.the.external.GTXCLK125.and.does.not.follow.the) 1779 0 R (M9.41131.TBItemNum.2.Data.output.measurement.point) 1780 0 R (M9.41520.TBItemNum.4.The.DDR.data.rate.is.2x.the.DDR.memory.bus.frequency) 1781 0 R
(M9.41844.FigTitle.Figure43.AC.Test.Load) 1782 0 R (M9.42174.TBItemNum.2.See.the.timing.measurement.conditions.in.the.PCI.22.Local.Bus.Specifications) 1783 0 R (M9.42675.TBTitle.Table46.Package.Thermal.Characteristics) 1784 0 R (M9.42680.TBItemNum.2.All.timings.are.in.reference.to.falling.edge.of.LCLK0.for.all.outputs.and.for.L) 1785 0 R (M9.42785.FigTitle.Figure9.Local.Bus.Signals.non.special.signals.only.DLL.Bypass.mode) 1786 0 R
(M9.43271.TBTitle.Table30.GPIO.Input.AC.Timing.Specifications.1) 1787 0 R (M9.43645.TBItemNum.1.GVDD.is.expected.to.be.within.50.mV.of.the.DRAM.GVDD.at.all.times) 1788 0 R (M9.43668.TBItemNum.4.Input.timings.are.measured.at.the.pin) 1789 0 R (M9.43865.TBItemNum.4.Input.timings.are.measured.at.the.pin) 1790 0 R (M9.44987.TBTitle.Table7.RESET.Initialization.Timing.Specifications) 1791 0 R
(M9.45801.TBTitle.Table17.RGMII.and.RTBI.AC.Timing) 1792 0 R (M9.45801.TBTitle.Table82.System.PLL.Multiplication.Factors) 1793 0 R (M9.46313.Heading3.185.Connection.Recommendations) 1794 0 R (M9.47011.TBItemNum.3.VTT.is.not.applied.directly.to.the.device.It.is.the.supply.to.which.far.end.sig) 1795 0 R (M9.47161.TBTitle.Table49.USB.DC.Electrical.Characteristics) 1796 0 R
(M9.47184.TBTitle.Table1.Revision.History) 1797 0 R (M9.47263.TBTitle.Table32.Local.Bus.DC.Electrical.Characteristics) 1798 0 R (M9.47426.TBTitle.Table38.IPIC.DC.Electrical.Characteristics) 1799 0 R (M9.47509.TBItemNum.3.Inputs.need.to.be.stable.at.least.one.TMR.clock) 1800 0 R (M9.47799.TBItemNum.5.In.rev.20.silicon.due.to.errata.tPCIXKH.minimum.is.1.ns.Refer.to.Errata.PCI17.i) 1801 0 R
(M9.48054.TBTitle.Table3.RESET.Timing.Specifications) 1802 0 R (M9.48237.Heading4.1414.Output.Driver.Characteristics) 1803 0 R (M9.48687.FigTitle.Figure8.GMII.Receive.AC.Timing) 1804 0 R (M9.48819.TBItemNum.3.In.rev.20.silicon.due.to.errata.tGTKHDX.minimum.and.tGTKHDV.maximum.are.not.sup) 1805 0 R (M9.49041.TBTitle.Table40.e300.Core.PLL.Configuration.) 1806 0 R
(M9.49718.TBItemNum.6.In.rev.20.silicon.due.to.errata.tPCIXKH.minimum.is.1.ns.Refer.to.Errata.PCI17.i) 1807 0 R (M9.50012.TBItemNum.2.The.csbclk.is.determined.by.the.CLKIN.and.system.PLL.ratio.See.Section22.Clocki) 1808 0 R (M9.50354.TBItemNum.1.This.parameter.is.sampled.GVDD..25.V..0125.V.f..1.MHz.TA..25C.VOUT..GVDD2.VOUT.) 1809 0 R (M9.51651.Heading2.5.RESET.Initialization) 1810 0 R (M9.52278.FigTitle.Figure31.PCIPCIX.Output.AC.Timing.Measurement.Condition) 1811 0 R
(M9.52401.TBItemNum.5.Thermal.resistance.between.the.die.and.the.case.top.surface.as.measured.by.the.) 1812 0 R (M9.52849.TBItemNum.9.In.rev.20.silicon.tDDKHMH.maximum.meets.the.specification.of.06.ns.In.rev.20.si) 1813 0 R (M9.53142.FigTitle.Figure9.MII.Transmit.AC.Timing) 1814 0 R (M9.53268.Heading3.1132.Mechanical.Dimensions.of.the.MPC8560.FCPBGA) 1815 0 R (M9.53426.TBItemNum.6.OVIN.on.the.PCI.interface.may.overshootundershoot.according.to.the.PCI.Electric) 1816 0 R
(M9.53692.TBItemNum.3.In.rev.20.silicon.due.to.errata.tTTKHDX.minimum.is.07.ns.for.UCC1.Refer.to.Erra) 1817 0 R (M9.53919.Heading3.22.Power.Sequencing) 1818 0 R (M9.54098.TBTitle.Table22.DDR.and.DDR2.SDRAM.Input.AC.Timing.Specifications.Mode.for.GVDDtyp25.V) 1819 0 R (M9.54704.FigTitle.Figure1.MPC8360E.Block.Diagram) 1820 0 R (M9.55385.TBItemNum.6.tLBOTOT2.should.be.used.when.RCWHLALE.is.set.and.when.the.load.on.LALE.output.p) 1821 0 R
(M9.55479.TBItemNum.2.Setup.and.hold.time.of.even.numbered.RCG.are.measured.from.riding.edge.of.PMARX) 1822 0 R (M9.55775.Example.Example1.Sample.Table.Use) 1823 0 R (M9.56030.TBItemNum.4.Input.timings.are.measured.at.the.pin) 1824 0 R (M9.56449.TBTitle.Table53.Utopia.DC.Electrical.Characteristics) 1825 0 R (M9.56468.FigTitle.Figure34.GPIO.AC.Test.Load) 1826 0 R
(M9.56487.Heading3.211.Package.Parameters.for.the.TBGA.Package) 1827 0 R (M9.56678.TBItemNum.2.GTXCLK125.is.used.to.generate.the.GTX.clock.for.the.UCC.Ethernet.transmitter.wi) 1828 0 R (M9.56810.TBItemNum.1.This.parameter.is.sampled.GVDD..18.V..0090.V.f..1.MHz.TA.25C.VOUT..GVDD2.VOUT.p) 1829 0 R (M9.57385.FigTitle.Figure7.GMII.Transmit.AC.Timing) 1830 0 R (M9.57402.TBItemNum.3.The.bit.rate.limit.is.independent.of.the.data.bus.width.that.is.the.same.for.se) 1831 0 R
(M9.57602.FigTitle.Figure42.TDMSI.AC.Timing..External.Clock.Diagram) 1832 0 R (M9.57657.FigTitle.Figure53.MPC8360E.Clock.Subsystem) 1833 0 R (M9.57897.TBTitle.Table4.MPC8349E.Typical.IO.Power.Dissipation) 1834 0 R (M9.58088.Heading2.19.Document.Revision.History) 1835 0 R]
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/Limits [(M9.58259.Heading4.823.RMII.AC.Timing.Specifications) (M9.75265.FigTitle.Figure45.Utopia.AC.Timing.Internal.Clock.Diagram)]
/Names [(M9.58259.Heading4.823.RMII.AC.Timing.Specifications) 1836 0 R (M9.59017.Heading4.212.Power.Supply.Voltage.Specification) 1837 0 R (M9.59176.Heading2.14.Electrical.and.Thermal.Characteristics) 1838 0 R (M9.59535.TBTitle.Table11.GMII.Transmit.AC.Timing.Specifications) 1839 0 R (M9.59591.TBTitle.Table11.DUART.AC.Timing.Specifications) 1840 0 R
(M9.59592.TBTitle.Table60.UART.AC.Timing.Specifications1) 1841 0 R (M9.59627.FigTitle.Figure40.Mechanical.Dimensions.and.Bottom.Surface.Nomenclature.of.the.MPC85460.FCP) 1842 0 R (M9.60266.FigTitle.Figure12.TBI.Receive.AC.Timing) 1843 0 R (M9.60410.TBItemNum.1.The.timer.can.operate.on.rtcclock.or.tmrclock.These.clocks.get.muxed.and.any.on) 1844 0 R (M9.60726.TBItemNum.5.MLOVIN.and.MVREF.may.overshootundershoot.to.a.voltage.and.for.a.maximum.duratio) 1845 0 R
(M9.61241.TBItemNum.2.abcHRESET.and.SRESET.are.open.drain.pins.thus.VOH.is.not.relevant.for.those.pin) 1846 0 R (M9.62739.FigTitle.Figure6.Timing.Diagram.for.tAOSKEW.Measurement) 1847 0 R (M9.62880.TBTitle.Table46.IPIC.Input.AC.Timing.Specifications.1) 1848 0 R (M9.63161.TBItemNum.5.The.local.bus.frequency.is.12.14.or.18.of.the.lbclk.frequency.depending.on.LCRR) 1849 0 R (M9.63371.TBItemNum.2.The.operating.conditions.for.junction.temperature.TJ.on.the.600333400MHz.and.50) 1850 0 R
(M9.63411.TBItemNum.5.Maximum.power.is.based.on.a.voltage.of.VDD..13.V.for.applications.that.use.667M) 1851 0 R (M9.64086.TBItemNum.2.Rise.and.fall.times.for.CLKINPCICLK.are.measured.at.04.V.and.27.V) 1852 0 R (M9.64163.TBTitle.Table44.Frequency.options.with.100.MHz.Memory.bus) 1853 0 R (M9.64236.TBItemNum.3.Thermal.solutions.will.likely.need.to.design.to.a.value.higher.than.typical.pow) 1854 0 R (M9.64853.TBTitle.Table441.Configurable.Clock.Units) 1855 0 R
(M9.65383.FigTitle.Figure13.AC.Test.Load) 1856 0 R (M9.65649.Heading3.1171.System.PLL.Configuration) 1857 0 R (M9.65665.Heading3.187.Pullup.Resistor.Requirements) 1858 0 R (M9.65861.FigTitle.Figure41.USB.AC.Test.Load) 1859 0 R (M9.66104.Heading3.11.Overview) 1860 0 R
(M9.66223.TBTitle.Table33.1588.Timer.AC.Specifications) 1861 0 R (M9.66319.TBItemNum.3.All.signals.are.measured.from.OVDD2.of.the.rising.edge.of.LSYNCIN.to.04OVDD.of.) 1862 0 R (M9.67264.TBItemNum.1.DDR.output.impedance.values.for.half.strength.mode.are.verified.by.design.and.n) 1863 0 R (M9.67556.TBTitle.Table31.SPI.DC.Electrical.Characteristics) 1864 0 R (M9.68150.TBItemNum.2.The.667.MHz.core.frequency.is.based.on.a.13V.VDD.supply.voltage) 1865 0 R
(M9.68362.FigTitle.Figure15.Driver.Impedance.Measurement) 1866 0 R (M9.68440.Heading3.1172.Core.PLL.Configuration) 1867 0 R (M9.68634.TBItemNum.2.Maximum.possible.skew.between.a.data.strobe.MDQSn.and.any.corresponding.bit.of.) 1868 0 R (M9.69012.TBItemNum.6.Typical.power.is.based.on.a.voltage.of.VDD..13.V.a.junction.temperature.of.TJ..) 1869 0 R (M9.69290.TBTitle.Table9.DDR2.SDRAM.Capacitance.for.GVDDtyp18.V) 1870 0 R
(M9.69310.Heading2.17.TDMSI) 1871 0 R (M9.69467.TBItemNum.4.Maximum.power.is.based.on.a.voltage.of.VDD..12.V.WC.process.a.junction.TJ..105C) 1872 0 R (M9.69694.TBTitle.Table41.Impedance.Characteristics) 1873 0 R (M9.69775.TBItemNum.3.POR.config.signals.consists.of.CFGRESETSOURCE02.and.CFGCLKINDIV) 1874 0 R (M9.69808.TBItemNum.1.AC.timing.values.are.based.on.the.DDR.data.rate.which.is.twice.the.DDR.memory.b) 1875 0 R
(M9.70134.FigTitle.Figure3.Maximum.AC.Waveforms.on.PCI.interface.for.33.V.Signaling) 1876 0 R (M9.70136.TBTitle.Table14.DDR.SDRAM.Input.AC.Timing.Specifications.for.18V.Interface) 1877 0 R (M9.70394.TBItemNum.1.GMIIMII.pins.that.are.not.needed.for.RGMII.RMII.or.RTBI.operation.are.powered.b) 1878 0 R (M9.70450.TBItemNum.4.Output.leakage.is.measured.with.all.outputs.disabled.0.V..VOUT..GVDD) 1879 0 R (M9.70474.TBItemNum.1.Caution.The.system.core.USB.security.and.101001000.Ethernet.must.not.exceed.the) 1880 0 R
(M9.70511.TBTitle.Table12.GMII.Receive.AC.Timing) 1881 0 R (M9.70829.TBItemNum.4.Duty.cycle.may.be.stretchedshrunk.during.speed.changes.or.while.transitioning.t) 1882 0 R (M9.70858.Heading3.1133.Pinout.Listings) 1883 0 R (M9.70908.TBItemNum.2.The.middle.of.a.start.bit.is.detected.as.the.eighth.sampled.0.after.the.1to0.tr) 1884 0 R (M9.71339.TBItemNum.4.These.JTAG.pins.have.weak.internal.pullup.PFETs.that.are.always.enabled) 1885 0 R
(M9.71577.Heading3.152.Ethernet.Management.Interface.Electrical.Characteristics) 1886 0 R (M9.72159.Heading4.221.PowerUp.Sequencing) 1887 0 R (M9.72597.TBItemNum.1.abcThis.table.applies.for.pins.PORESET.HRESET.SRESET.and.QUIESCE) 1888 0 R (M9.72852.TBItemNum.8.For.purposes.of.activefloat.timing.measurements.the.HiZ.or.offstate.is.defined.) 1889 0 R (M9.72987.TBItemNum.5.Note.that.tDDKHMH.follows.the.symbol.conventions.described.in.note.1.For.exampl) 1890 0 R
(M9.73023.TBTitle.Table19.Local.Bus.General.Timing.Parameters.DLL.on) 1891 0 R (M9.73264.TBItemNum.2.MVREF.is.expected.to.equal.05..GVDD.and.to.track.GVDD.DC.variations.as.measured) 1892 0 R (M9.73891.TBItemNum.4.TDM.in.highspeed.mode.for.serial.data.interface) 1893 0 R (M9.73965.TBTitle.Table23.RMII.Transmit.AC.Timing.Specifications) 1894 0 R (M9.73986.TBItemNum.2.These.are.asynchronous.signals) 1895 0 R
(M9.74519.Heading4.0011.GMIIRGMIIRTBIRTBI.Electrical.Characteristics) 1896 0 R (M9.74764.Heading2.19.JTAG.Timing.Specifications) 1897 0 R (M9.74890.TBItemNum.3.This.output.is.actively.driven.during.reset.rather.than.being.threestated.durin) 1898 0 R (M9.75265.FigTitle.Figure45.Utopia.AC.Timing.Internal.Clock.Diagram) 1899 0 R]
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/Limits [(M9.75412.FigTitle.Figure5.DDR.AC.Test.Load) (M9.87855.TBTitle.Table31.PCIPCIX.DC.Electrical.Characteristics.1)]
/Names [(M9.75412.FigTitle.Figure5.DDR.AC.Test.Load) 1900 0 R (M9.75469.TBItemNum.2.CB..capacitance.of.one.bus.line.in.pF) 1901 0 R (M9.75721.TBItemNum.2.All.timings.are.in.reference.to.rising.edge.of.LSYNCIN) 1902 0 R (M9.75742.TBItemNum.4.Input.timings.are.measured.at.the.pin) 1903 0 R (M9.75891.TBItemNum.6.tLBOTOT2.should.be.used.when.RCWHLALE.is.set.and.when.the.load.on.LALE.output.p) 1904 0 R
(M9.75968.TBItemNum.3.Timing.is.guaranteed.by.design.and.characterization) 1905 0 R (M9.76231.TBItemNum.15.This.pin.must.always.be.tied.to.GVDD) 1906 0 R (M9.76525.Heading2.115.SPI) 1907 0 R (M9.76835.TBItemNum.2.MVREF.is.expected.to.be.equal.to.05..GVDD.and.to.track.GVDD.DC.variations.as.me) 1908 0 R (M9.77145.TBItemNum.9.These.are.On.Die.Termination.pins.used.to.control.DDR2.memories.internal.termin) 1909 0 R
(M9.77257.TBItemNum.7.All.outputs.are.referenced.to.the.rising.edge.of.MCKn.at.the.pins.of.the.device) 1910 0 R (M9.77309.TBItemNum.3.All.signals.are.measured.from.OVDD2.of.the.risingfalling.edge.of.LCLK0.to.04OVD) 1911 0 R (M9.77418.FigTitle.Figure6.DDR.SDRAM.Output.Timing.Diagram) 1912 0 R (M9.77749.TBTitle.Table21.Local.Bus.DC.Electrical.Characteristics) 1913 0 R (M9.78159.TBItemNum.2.This.pin.is.an.open.drain.signal.A.weak.pullup.resistor.210.kW.should.be.placed) 1914 0 R
(M9.78259.TBItemNum.2.tCLKIN.is.the.clock.period.of.the.input.clock.applied.to.CLKIN.It.is.only.valid) 1915 0 R (M9.78448.TBItemNum.5.NonJTAG.signal.output.timing.with.respect.to.tTCLK) 1916 0 R (M9.78471.TBItemNum.1.Junction.temperature.is.a.function.of.die.size.onchip.power.dissipation.package) 1917 0 R (M9.78551.TBTitle.Table56.HDLC.BiSync.Transparent.and.UART.AC.Timing.Specifications1) 1918 0 R (M9.78768.Heading2.113.PLL) 1919 0 R
(M9.78933.TBItemNum.2.This.implies.that.PC.board.design.will.require.clocks.to.be.routed.such.that.an) 1920 0 R (M9.78936.TBItemNum.2.This.pin.is.an.open.drain.signal.A.weak.pullup.resistor.210.kW.should.be.placed) 1921 0 R (M9.79003.TBTitle.Table8.DDR2.SDRAM.DC.Electrical.Characteristics.for.GVDDtyp18.V) 1922 0 R (M9.79036.Heading4.2324.Heat.Sinks.and.JunctiontoAmbient.Thermal.Resistance) 1923 0 R (M9.79193.TBTitle.Table19.MII.Management.DC.Electrical.Characteristics) 1924 0 R
(M9.79213.TBTitle.Table13.MII.Transmit.AC.Timing.Specifications) 1925 0 R (M9.79278.TBItemNum.2.All.MCKMCK.referenced.measurements.are.made.from.the.crossing.of.the.two.signal) 1926 0 R (M9.79322.TBTitle.Table64.PPC8358ESC8358EMPC8358E.TBGA.Pinout.Listing) 1927 0 R (M9.79524.Heading2.16.Ethernet.3.Speed.10100.MII.Management) 1928 0 R (M9.79539.TBItemNum.6.Determined.by.maximum.possible.skew.between.a.data.strobe.MDQS.and.any.correspo) 1929 0 R
(M9.79934.TBTitle.Table47.SPI.DC.Electrical.Characteristics) 1930 0 R (M9.79978.TBItemNum.2.Per.JEDEC.JESD512.and.SEMI.G3887.with.the.single.layer.board.horizontal) 1931 0 R (M9.80072.TBItemNum.7.tLBOTOT3.should.be.used.when.RCWHLALE.is.set.and.when.the.load.on.LALE.output.p) 1932 0 R (M9.80092.TBTitle.Table5.Input.AC.Timing.Parameters.for.DDR.SDRAM.Interface) 1933 0 R (M9.81124.TBItemNum.4.This.represents.the.total.input.jittershort.term.and.long.termand.is.guaranteed) 1934 0 R
(M9.81172.Heading2.113.Thermal.Specifications) 1935 0 R (M9.81244.TBItemNum.3.For.10.and.100.Mbps.tRGT.scales.to.400.ns..40.ns.and.40.ns..4.ns.respectively) 1936 0 R (M9.81256.TBItemNum.12.Refers.to.MPC8360E.PowerQUICC.II.Pro.Integrated.Communications.Processor.Famil) 1937 0 R (M9.81732.TBTitle.Table30.I2C.AC.Electrical.Characteristics) 1938 0 R (M9.82007.TBItemNum.4.Thermal.resistance.between.the.die.and.the.printedcircuit.board.per.JEDEC.JESD5) 1939 0 R
(M9.82349.TocInTxt.18.System.Design.Information.103) 1940 0 R (M9.83032.FigTitle.Figure41.TDMSI.AC.Test.Load) 1941 0 R (M9.83354.FigTitle.Figure33.PCI.AC.Test.Load) 1942 0 R (M9.83511.TBItemNum.7.tLBOTOT3.should.be.used.when.RCWHLALE.is.set.and.when.the.load.on.LALE.output.p) 1943 0 R (M9.83721.FigTitle.Figure43.Utopia.AC.Test.Load) 1944 0 R
(M9.83915.FigTitle.Figure10.MII.Receive.AC.Timing) 1945 0 R (M9.84203.TBItemNum.7.In.rev.20.silicon.due.to.errata.tSKRGTKHDX.minimum.is.23.ns.and.tSKRGTKHDV.maxi) 1946 0 R (M9.84315.Heading3.172.Local.Bus.AC.Electrical.Specifications) 1947 0 R (M9.84473.TBItemNum.9.This.frequency.combination.is.not.available.for.rev.20.silicon) 1948 0 R (M9.85035.TBItemNum.1.This.specification.applies.when.operating.from.33V.supply) 1949 0 R
(M9.85307.TBTitle.Table69.Operating.Frequencies.for.the.TBGA.Package) 1950 0 R (M9.85499.TBItemNum.5.tLBOTOT1.should.be.used.when.RCWHLALE.is.not.set.and.when.the.load.on.LALE.outp) 1951 0 R (M9.85988.Heading2.113.Timers) 1952 0 R (M9.86002.Heading3.101.JTAG.DC.Electrical.Characteristics) 1953 0 R (M9.86167.TBTitle.Table54.Utopia.AC.Timing.Specifications.1) 1954 0 R
(M9.86346.TBItemNum.2.This.symbol.is.used.to.represent.the.external.GTXCLK125.signal.and.does.not.fol) 1955 0 R (M9.86388.TBTitle.Table55.HDLC.BiSync.Transparent.and.UART.DC.Electrical.Characteristics) 1956 0 R (M9.86762.Heading3.53.QE.Operating.Frequency.Limitations) 1957 0 R (M9.86891.TBItemNum.6.Thermal.characterization.parameter.indicating.the.temperature.difference.betwee) 1958 0 R (M9.87474.TBItemNum.15.It.is.recommended.that.MDIC0.be.tied.to.GND.using.an.182W.resistor.and.MDIC1.b) 1959 0 R
(M9.87532.TBItemNum.12.Refers.to.MPC8360E.PowerQUICC.II.Pro.Integrated.Communications.Processor.Famil) 1960 0 R (M9.87697.Heading4.811.101001000.Ethernet.DC.Electrical.Characteristics) 1961 0 R (M9.87744.TBTitle.Table4.DDR.Capacitance) 1962 0 R (M9.87855.TBTitle.Table31.PCIPCIX.DC.Electrical.Characteristics.1) 1963 0 R]
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/Limits [(M9.88127.Heading4.825.RGMII.and.RTBI.AC.Timing.Specifications) (P.23)]
/Names [(M9.88127.Heading4.825.RGMII.and.RTBI.AC.Timing.Specifications) 1964 0 R (M9.88503.TBItemNum.3.The.500MHz.QE.frequency.is.based.on.a.13V.VDD.supply.voltage) 1965 0 R (M9.88576.FigTitle.Figure44.AC.Timing.External.Clock.Diagram) 1966 0 R (M9.88586.TBItemNum.6.This.symbol.is.used.to.represent.the.external.GTXCLK125.and.does.not.follow.the) 1967 0 R (M9.88643.TBTitle.Table8.GMII.MII.and.TBI.Pins.DC.Specification) 1968 0 R
(M9.88755.TBTitle.Table5.Drive.Capability.of.MPC8245.Output.Pins.5) 1969 0 R (M9.89142.TBItemNum.3.For.purposes.of.activefloat.timing.measurements.the.HiZ.or.offstate.is.defined.) 1970 0 R (M9.89680.TBItemNum.3.This.parameter.is.dependent.on.the.ceclk.speed.that.is.for.a.ceclk.of.200MHz.th) 1971 0 R (M9.89948.Heading4.822.MII.AC.Timing.Specifications) 1972 0 R (M9.90089.TBTitle.Table3.I2C.DC.Electrical) 1973 0 R
(M9.90450.TBItemNum.10.This.pin.must.always.be.tied.to.GND) 1974 0 R (M9.90569.TBItemNum.4.Output.leakage.is.measured.with.all.outputs.disabled.0.V..VOUT..GVDD) 1975 0 R (M9.91023.TBItemNum.7.Maximum.power.is.based.on.a.voltage.of.VDD..13.V.for.applications.that.use.667M) 1976 0 R (M9.91288.TBItemNum.4.ADDRCMD.includes.all.DDR.SDRAM.output.signals.except.MCKMCK.MCS.and.MDQMECCMDMM) 1977 0 R (M9.91567.TBItemNum.3.Per.JEDEC.JESD516.with.the.board.horizontal.1.msec.is.approximately.equal.to.20) 1978 0 R
(M9.91627.TBTitle.Table5) 1979 0 R (M9.91693.Heading2.15.IPIC) 1980 0 R (M9.91778.TBItemNum.3.In.the.source.synchronous.mode.MCKMCK.can.be.shifted.in..applied.cycle.incremen) 1981 0 R (M9.91904.Heading3.152.DDR.SDRAM.AC.Electrical.Characteristics) 1982 0 R (M9.91944.TBTitle.Table27.Timers.DC.Electrical.Characteristics) 1983 0 R
(M9.91944.TBTitle.Table50.System.PLL.Multiplication.Factors) 1984 0 R (M9.92011.FigTitle.Figure27.SPI.AC.Timing.in.Slave.mode.External.Clock.Diagram) 1985 0 R (M9.92408.FigTitle.Figure30.PCIPCIX.Input.AC.Timing.Measurement.Conditions) 1986 0 R (M9.92812.TBItemNum.1.This.pin.is.an.open.drain.signal.A.weak.pullup.resistor.1.kW.should.be.placed.o) 1987 0 R (M9.93128.TBItemNum.11.This.pin.must.always.be.left.not.connected) 1988 0 R
(M9.93180.TBItemNum.1.GVDD.is.expected.to.be.within.50.mV.of.the.DRAM.GVDD.at.all.times) 1989 0 R (M9.93429.TBTitle.Table63.PPC8360EMPC8360E.TBGA.Pinout.Listing) 1990 0 R (M9.93967.TBTitle.Table2.Recommended.Operating.Conditions) 1991 0 R (M9.94488.TBItemNum.4.NonJTAG.signal.input.timing.with.respect.to.tTCLK) 1992 0 R (M9.95430.TBTitle.Table7.ECGTXCLK125.AC.Timing.Specifications) 1993 0 R
(M9.96144.FigTitle.Figure3.DDR.Input.Timing.Diagram) 1994 0 R (M9.96173.Heading2.15.DUART) 1995 0 R (M9.96293.TBTitle.Table51.Suggested.PLL.Configurations.CFGCLKINDIV..0.LBIUCM..0.DDRCM..0) 1996 0 R (M9.96657.Heading2.5.RESET.Initialization) 1997 0 R (M9.96908.Heading2.20.UtopiaPOS.DC.Electrical.Characteristics) 1998 0 R
(M9.97099.TBItemNum.1.Output.voltage.open.drain.or.open.collector.condition..3.mA.sink.current) 1999 0 R (M9.97200.FigTitle.Figure14.MII.Management.Interface.Timing) 2000 0 R (M9.97258.TBTitle.Table57.Heat.Sinks.and.JunctiontoCase.Thermal.Registance.of.MPC8349EMPC8347E.TBGA) 2001 0 R (M9.97549.FigTitle.Figure20.Local.Bus.Signals.GPCMUPM.Signals.for.LCCRCLKDIV..2.DLL.Bypass.Mode) 2002 0 R (M9.98198.TBTitle.Table15.TBI.Transmit.AC.Timing.at.Recommended.Operating.Conditions) 2003 0 R
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